The trend in the semiconductor industry is toward smaller devices so that higher density circuits can be fabricated on a single chip. The miniaturization of transistor devices and circuits can be achieved in the field effect transistor (FET) family of circuits partly by reducing the size of the various masks used in the semiconductor fabrication process. This technique is termed "scaling" and is implemented by reducing the size of all the features of the surface-oriented devices so that the resultant devices occupy a smaller surface area of the wafer.
In order to achieve devices with higher packing density, it is important to shrink not only the channel length but also the channel width for the planar transistor. However, planar narrow width transistors exhibit problems such as, threshold voltage variation, increase of substrate bias effect due to impurity concentration enhancement in the channel region, and reliability degradation by hot-carriers. The narrow width transistors also cause decrease of current drivability and reliability degradation due to the large electric field at the LOCOS edge. To realize a high packing density without reducing a feature size, such as channel width, vertical transistors have been fabricated. In the vertical transistor the gate electrode surrounds a pillar of silicon whose sidewalls are used as the channel. Since the pillar can have four sides, it is noted that the channel width of the vertical transistor can be four times that of a planar transistor occupying the same silicon area. Other advantages of a vertical transistor include ease of forming a short channel length transistor without severe lithography constraints as in the fabrication of a short channel length planar transistor.